Method and system for false path analysis
US7216318B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Jan 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods and systems for performing false path analysis. In one approach, the methods and systems identify a set of zero or more false paths based upon both implementation-specific design data and non-implementation-specific design data. In some approaches, disclosed are methods and systems for performing automated gate-level static timing false path analysis, identification, constraint generation, and/or verification using architectural information. Static timing paths at the gate-level can be linked to the architectural information via mapping techniques found in equivalence checking (EC). The gate level static timing paths can be analyzed in the context of the architectural information to identify false paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.