High-yield single-level gate charge-coupled device design and fabrication
US7217601B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2003 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Dec 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D44/45
Abstract
In accordance with the invention, an electrically conducting charge transfer channel is formed in a semiconductor substrate and an electrically insulating layer is formed on a surface of the substrate; a layer of gate electrode material is formed on the insulating layer. On the gate material layer is formed a first patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gate electrodes, and the first-pattern-exposed regions of the gate material layer are electrically doped. In addition, on the gate material layer is formed a second patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gaps between gate electrodes, and the second-pattern-exposed regions of the gate material layer are etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.