Technique for suppression of edge current in semiconductor devices
US7217953B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2004 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | May 18, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
Abstract
A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.