Switch matrix circuit, logical operation circuit, and switch circuit
US7218142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2004 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Nov 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.