Method of adjusting sampling condition of analog to digital converter and apparatus thereof
US7218261B2 · kind B2 · utility
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6References
22Claims
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Key dates
| Filing date | Jan 5, 2006 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Jan 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.