Devices and systems for electrostatic discharge suppression
US7218492B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 2004 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Jan 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0738
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A device (10) for suppressing electrostatic discharge comprises first and second multilayer structures (14, 16) surrounding an electrostatic discharge reactance layer (12), the resistance of said electrostatic discharge reactance layer (12) varying in response to the occurrence of an electrostatic discharge signal. Each multilayer structure (14, 16) comprises a barrier layer (18), a terminal layer (20) and an electrode layer (28). Alternatively, a conductive layer (80) can be used instead of a second multilayer structure (16). An ESD suppression device (110) can be embedded in a printed circuit board (122, 210) providing a way to protect board components from harmful ESD events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.