Reconfigurable trace cache
US7219207B2 · kind B2 · utility
6Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Apr 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.