Digital system having selectable clock speed based upon available supply voltage and PLL configuration register settings
US7219246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2004 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Oct 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Clock speed is controlled based upon the supply voltage to a digital device. When the supply voltage is below a reference voltage the clock speed will be slower than if the supply voltage is above the reference voltage. A phase-lock-loop (PLL) may be used to generate a higher frequency that is an integer multiple of a reference oscillator. The clock speed will be proportional to the frequency multiplication of the PLL when the faster clock speed is selected. A multiplexer is used to switch between different frequency sources, and a timer can be used to insure stable operation of the PLL. A status configuration register has status and control bits for indicating and controlling operation of the clock speed control. A universal serial bus (USB) device can operate at a slower clock with reduced operating voltage, and at a faster clock with increased operating voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.