System and method for verifying a layout of circuit traces on a motherboard
US7219318B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Aug 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for verifying a layout of circuit traces on a motherboard includes a computer (1) and a database (2). The database is used for storing data generated and used by the system. The computer includes: a substandard layout area creating module (101) for creating substandard layout areas; a substandard segment data obtaining module (102) for obtaining from the database actual layout data on substandard segments placed in the substandard areas; a substandard length calculating module (103) for calculating a total length of all the substandard segments of a trace; and a satisfactory trace determining module (104) for comparing the total length of the substandard segments of the trace with a preset standard length for the trace, and determining whether the trace is satisfactory. A related method is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.