Planarization with reduced dishing
US7220362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2006 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Jan 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.