WAT process to avoid wiring defects
US7220677B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2005 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Aug 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.