Thin film transistor array panel and a liquid crystal display including the same
US7220992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2005 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Nov 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel is provided, which includes: a substrate; a plurality of first signal lines formed on the substrate; a plurality of second signal lines intersecting, and insulated from, the first signal lines; a plurality of pixel electrodes formed in intersection areas of the first and second signal lines; a plurality of first thin film transistors electrically connected to the first signal lines, the second signal lines, and the pixel electrodes; a plurality of buffer electrodes capacitively coupled to the pixel electrodes and located at a boundary of the intersection areas; and a plurality of second thin film transistors electrically connected to the buffer electrodes and the first signal lines, wherein the first signal lines are connected to the pixel electrodes of a previous row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.