Circuit and method for storing data in operational, diagnostic and sleep modes
US7221205B2 · kind B2 · utility
8Cited by
10References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 6, 2004 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Nov 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 through a transmission gate 22 (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop 2 to move into and out of sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.