Reference timing architecture
US7221687B2 · kind B2 · utility
24Cited by
8References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 17, 2002 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | May 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A reference timing architecture is disclosed that provides a level of flexibility that was not available with the architecture in the prior art. In particular, the present invention provides for multiple reference timing outputs that can be routed to equipment nodes relying on the timing information, wherein each of the timing processing paths that provide timing outputs can be controlled independently of one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.