Cache residency test instruction
US7222217B2 · kind B2 · utility
12Cited by
8References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Jun 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache residency test instruction is described which, when executed by a processor unit, allows the processor unit to determine if a set of data resides in a cache memory that is communicatively coupled to the processor unit and communicate a result of the determination to software being executed on the processor unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.