Channel processor using reduced complexity LDPC decoder
US7222289B2 · kind B2 · utility
17Cited by
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21Claims
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Key dates
| Filing date | Sep 30, 2003 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Jan 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-density parity check device can process data using a special low-density parity check matrix having a size of n-rows by m-columns. By styling the matrix such that the matrix is composed of p equal-size sqaure sub-matrices, only the first row of the first sub-matrix need be generated and stored. By then further constraining each of the sub-matrices to form various sub-portions, with each sub-portion constructed such that any two columns within the sub-portion will have no common location containing a non-zero entry, processing advantages are gained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.