Hardware-based HDL code coverage and design analysis
US7222315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Jan 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs. Moreover, various embodiments related to HDL code coverage are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.