Test structures in unused areas of semiconductor integrated circuits and methods for designing the same
US7223616B2 · kind B2 · utility
85Cited by
6References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Aug 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.