MOS transistors and methods of manufacturing the same
US7223663B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Feb 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.