Multi-level thin film capacitor on a ceramic substrate
US7224040B2 · kind B2 · utility
23Cited by
17References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Dec 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/16
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.