Secure processor architecture for use with a digital rights management (DRM) system on a computing device
US7225333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Aug 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/603
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A secure processor is operable in normal and preferred modes, and includes a security kernel instantiated when the processor enters into preferred mode and a security key accessible by the security kernel during preferred mode. The security kernel employs the accessed security key to authenticate a secure application, and allows the processor to be trusted to keep hidden a secret of the application. To instantiate the application, the processor enters preferred mode where the security key is accessible, and instantiates and runs the security kernel. The security kernel accesses the security key and applies same to decrypt a key for the application, stores the decrypted key in a location where the application will expect same, and instantiates the application. The processor then enters the normal mode, where the security key is not accessible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.