Method and apparatus for enabling a low power mode for a processor
US7225347B2 · kind B2 · utility
1Cited by
30References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Dec 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.