Circuit and method for aligning transmitted data by adjusting transmission timing for a plurality of lanes
US7225354B2 · kind B2 · utility
16Cited by
2References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Apr 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align transmitted data of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.