Method and apparatus for parallel computation of linear block codes
US7225391B1 · kind B1 · utility
9Cited by
8References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2002 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1595
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for generating a linear block code is disclosed. A message is broken up into a plurality of sets of bits. A first group of sets is processed to determine a first partial linear block code. An adjusted partial linear block code is generated from the partial linear block code. A second group of sets is processed to determine a second partial linear block code. The adjusted partial linear block code and the second partial linear block code are combined into a single value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.