Method and system to verify a circuit design by verifying consistency between two different language representations of a circuit design
US7225417B2 · kind B2 · utility
2Cited by
3References
39Claims
0Family size
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Key dates
| Filing date | Feb 5, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Jan 17, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to verify a circuit design may include applying a bounded model checking technique to a first computer language representation of the circuit design and to a second computer language representation of the circuit design. The method may also include determining a behavioral consistency between the first and second computer language representations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.