Low leakage and data retention circuitry
US7227383B2 · kind B2 · utility
15Cited by
19References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2005 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Mar 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.