Scan friendly domino exit and domino entry sequential circuits

US7227384B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mondira Pant · Westborough, US
• Paul Gronowski · Northborough, US
• Randy L. Allmon · North Grafton, US
• Manjunath Bhat · Thousand Oaks, US
• David Lin · Westborough, US

Key dates

• Filing date: Aug 11, 2005
• Grant date: Jun 5, 2007
• Expiry date: Jan 17, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318572
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.