Current source architecture for memory device standby current reduction
US7227804B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Nov 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device (200) can include a memory cell block (202), a standby current source (206), an active current source (208), and a clamping device (212). In a standby mode, a standby current source (206) can provide constant standby current ISTBY to memory cell block (202) via block supply node (204). In an active mode, active current source (208) can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit (212) can provide additional current in the event a block supply node (204) potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well (454) to source (404) back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (454), reducing overall leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.