Patent · US Expired

FIFO buffer depth estimation for asynchronous gapped payloads

US7227876B1 · kind B1 · utility

10Cited by

14References

38Claims

0Family size

Assignee

PMC-Sierra, Inc. · US

Inventors

Alexander Cochran · North Vancouver, CA
Patrick Bailey · Port Coquitlam, CA
Larrie Simon Carr · Kelowna, CA

Key dates

Filing date	Dec 18, 2002
Grant date	Jun 5, 2007
Priority date	—
Expiry date	Feb 2, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH04J3/076
WIPO fieldTelecommunications
WIPO sectorElectrical engineering

Abstract

A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer values Ii is repetitively consecutively produced during each consecutive one of j FIFO buffer write clock cycles, where i=1, . . . , j and where j and the integer values Ii are selected such thatclosely approximates the number of bits read from the FIFO buffer per FIFO buffer write clock cycle. During each kth consecutive FIFO buffer write clock cycle, a Bits_Read value Ik+Ik-1 is produced where k=1, . . . , p; a Bits_Written value is produced; a Gap_Pattern value is derived by subtracting the Bits_Read value from the Bits_Written value; and, the Gap_Pattern is added to a predefined value representative a FIFO buffer center fill level to produce the desired FIFO buffer fill level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.