Combined transmitter
US7228116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Oct 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit includes a set of first input terminals to receive first data, and a second (TMDS) transmission unit includes a set of second input terminals to receive second data. A phase locked loop (PLL) generates a first set of output clock signals to the first transmission unit in a first mode and a second set of output clock signals to the second transmission unit in a second mode according to a mode selection signal. The first and second transmission units are able to transmit the first data to the first and second external input units in the first and second modes respectively, according to the mode selection signal and the first and second sets of output clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.