Bypassable adder
US7228325B2 · kind B2 · utility
5Cited by
7References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2001 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Jul 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/462
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the second input (B), the logic circuit configured to hold at least one of the first input (A) and the second input (B) according to the bypass input (bypass).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.