Wireless data communications using FIFO for synchronization memory
US7228392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2003 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Dec 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/02
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.