Memory interleaving
US7228393B2 · kind B2 · utility
2Cited by
7References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Jun 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory sub-sections. A memory interlace controller interfaces a faster CPU to several sub-sections of slower memory. The memory interlace controller interlaces the access of the slower memory and thus optimizing the CPU system speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.