Digital visual interface
US7230460B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques or designs of circuits to correct distortions in signals transported over a high-speed digital connection between a video source (e.g., a PC or a DVD player) and a digital monitors (such as LCDs) are disclosed. According to one aspect of the present invention, a distorted signal is corrected by an interface circuit that oversamples the incoming signal with clock pulses or signals generated using a phase lock loop (PLL) from a clock seed signal. These clock signals possess different phases that are shifted from each other. In order to support a wide range of data rate, a programmable DPLL is used to produce a number of different ranges of clock frequency (e.g., 4 ranges). In addition, to avoid data phase shift, a delay locked loop (DLL) is used to compensate for the phase shift. A phase detection logic is also used to extract phase information from the over-sampled data. The phase information is fed back to the DLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.