Method and apparatus for an LNA with high linearity and improved gain control
US7230491B1 · kind B1 · utility
2Cited by
23References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2005 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Jul 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G2201/103
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bias circuit for biasing a linear input stage of an amplifier comprises a first MOS device having a size. A second MOS device has a size and is arranged with the first MOS device in a cascode configuration. The second MOS device is operated in a saturation region. A third MOS device has a size and biases the first MOS device in a triode region. A bias switch ratio of the size of the first MOS device to the size of the third MOS device is greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.