Floating-point type digital signal reversible encoding method, decoding method, apparatuses therefor, and programs therefor
US7230551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Jun 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/4087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Signal samples X in a floating-point format, each of which is composed of 1 bit of sign S, 8 bits of exponent E and 23 bits of mantissa M, are converted through truncation by an integer formatting part 12 into signal samples Y in a 24-bit integer format, the integer-value signal samples Y are coded by a compressing part 13 into a code sequence Ca, and the code sequence Ca is output. According to the number of digits n following the most significant “1” in the integer-value signal sample Y, a difference producing part 14 extracts the least significant (23−n) bits from the mantissa M of the input signal sample X to form a difference signal Z, and a compressing part 17 performs entropy coding of the difference signal Z to produce a code sequence Cb and outputs the code sequence Cb. Alternatively, the difference signal Z may be output as it is, rather than being compressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.