Repairable memory in display devices
US7230600B1 · kind B1 · utility
4Cited by
10References
43Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Mar 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A display system includes a repairable memory that re-routes data when a defect exists in the memory. A significant bit in the display memory that would otherwise be corrupted by a bad memory cell is re-routed to a least significant bit position in the memory, and the least significant information is discarded. The repairable memory includes a memory device and two repair routers. One repair router is on the input of the memory, and one repair router is on the output of the memory. One or more least significant bits can be sacrificed to preserve more significant bit information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.