Method and circuit for cascaded pulse width modulation
US7230837B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 27, 2006 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Mar 27, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E40/20
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of balancing the voltage of DC links in a cascaded multi-level converter (CMC) semiconductor circuit, including the steps of providing a plurality of H-bridge converters per phase in the CMC circuit and utilizing a three phase duty cycle value from the main controller to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value. The normalized duty cycle value and an output current of the CMC is used to determine the direction and polarity of a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages. A voltage summation result and direction is obtained from a ceiling index pointer and a floor index pointer and the voltage summation result, direction from the ceiling index pointer and a floor index pointer are used to create a combined switching table for the H-bridge converters. A pulse width modulator is utilized to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.