High-speed multiplexer latch
US7230856B1 · kind B1 · utility
2Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2005 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Oct 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer latch may further include an inverter having an input and an output. The input of the inverter is also coupled to the latch at the second node and the output of the inverter is coupled to a data output terminal. The multiplexer latch may further include a bypass circuit coupled to the latch at the first node and the data output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.