Fast locking clock and data recovery unit
US7231008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Dec 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of synchronizing a transmitter and a receiver, comprising: receiving a transmitted serial data stream. Creating an N-bit data sample from the serial data stream. Decoding the N-bit data sample by a ring decoding technique. The ring decoding technique comprises: creating a first code ring using the N-bit data sample, the first code ring having N ring-bit phase positions corresponding to N axis positions, with the N data bits of the N-bit data sample corresponding to one of the N ring-bit phase positions. Creating a pth Code Ring from a previous code ring using a preselected ring coding technique, the pth code ring having N ring-bit phase positions corresponding to N axis positions, with N data bits of the pth code ring corresponding to the N ring-bit phase positions of the pth code ring. Analyzing selected ones of the N data bits of the pth code ring for the presence of a sentinel condition. Identifying a one of the N ring-bit phase positions of the pth code ring as being associated with the sentinel condition. Selecting a clock signal based on the one of the N ring-bit phase positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.