Future activity list for peripheral bus host controller
US7231468B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2003 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Feb 2, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment includes a future activity list (FAL) maintained within a peripheral bus host controller. The FAL includes information indicating for a number of peripheral bus frames whether those frames will have activity or are null. For frames that will have activity, the host controller performs a system memory read to gather information required to process the active frame. For frames that are null, the host controller does not perform the system memory read. A bus master status bit is pegged (continually set to “true”) by the host controller only when the host controller is processing an active frame. Because the bus master status bit is not pegged by the host controller during null frames, there is greater opportunity for an operating system to enter lower power states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.