Advanced bandwidth allocation in PCI bus architecture
US7231475B1 · kind B1 · utility
24Cited by
16References
25Claims
0Family size
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Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Jul 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/3625
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus arbitration system and method allocates total bus bandwidth between latency sensitive and latency insensitive interfaces by utilizing windows to divide the total bandwidth into latency sensitive and latency insensitive portions. Each interface is initially allocated top-up numbers of latency sensitive and latency insensitive tokens to proportionally allocate bus accesses between the interfaces according to their requirements. For an interface having access to the bus, the number of tokens is decremented for each successful bus transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.