Method and memory controller for scalable multi-channel memory access
US7231484B2 · kind B2 · utility
5Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2003 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Sep 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrical device is connected to at least one memory accessing unit and to a memory including at least one physical memory module. The device includes at least one access channel circuit connected to the least one memory accessing unit via at least one system bus and to the at least one physical memory module. The access channel circuit provides memory access for the at least one memory accessing unit to at least a part of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.