Configurable finite state machine for operation of microinstruction providing execution enable control value
US7231508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2001 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Nov 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.