Wake-up reset circuit draws no current when a control signal indicates sleep mode for a digital device
US7231533B2 · kind B2 · utility
7Cited by
13References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Oct 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused unstable and unknown logic states in sequential circuit elements, e.g., volatile memory, flip flops and/or latching circuits. The wake-up reset circuit draws substantially no current when not generating the reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.