Reset circuit for resetting two clock domains
US7231539B1 · kind B1 · utility
3Cited by
4References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Aug 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset circuit for resetting two clock domains resets the two clock domains synchronously with a first clock signal in response to assertion of a system reset. It then de-asserts the resetting of a first of the clock domains in synchronization with the first clock signal, and de-asserts the resetting of a second of the clock domains in synchronization with a second clock signal so that the second clock domain is not operative until after the second clock signal is running.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.