Patent · US Expired

Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks

US7231567B2 · kind B2 · utility

0Cited by
4References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 27, 2004
Grant dateJun 12, 2007
Priority date—
Expiry dateApr 20, 2025

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318594
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode. The shift mode generally operates with multiple scan clocks that are clocked simultaneously. The capture mode generally operates with multiple scan clocks, but only one of which is toggled at a time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.