Method and circuit for parametric testing of integrated circuits with an exclusive-or logic tree
US7231572B2 · kind B2 · utility
3Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 15, 2005 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second input that is connected to an output of a preceding XOR gate to form an XOR logic tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.