Methods and apparatus for transforming sequential logic designs into equivalent combinational logic
US7231615B2 · kind B2 · utility
1Cited by
11References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Feb 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are novel methods and apparatus for transforming sequential logic designs into equivalent combinational logic. In an embodiment of the present invention, a design method for transforming sequential logic designs into equivalent combinational logic is disclosed. The design method includes: simulating each stage of a clocking sequence to produce simulation values; saving the simulation values; and performing a plurality of backward logic traces based on the saved simulation values to provide an equivalent combinational logic representation of a sequential logic design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.