Photo-imaged stress management layer for semiconductor devices
US7232692B2 · kind B2 · utility
3Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jun 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A photo-imaged stress management layer for a semiconductor device is described. The stress management layer is located on an outer surface of a semiconductor device and may be patterned to address certain stress compensation requirements of the semiconductor device. The stress management layer may be manufactured onto the semiconductor device using a photolithographic procedure that allows both simple and complex patterns to be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.